1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a single-polysilicon layer non-volatile memory string having a single-layer polysilicon floating gate and an operating method thereof.
2. Description of Related Art
When semiconductor fabrication process enters a domain of deep sub-micron, sizes of devices become smaller, so that regarding a memory device, sizes of memory cells thereof become more and more smaller. On the other hand, as data required to be processed and stored by information electronic products (such as computers, mobile phones, digital cameras or personal digital assistants (PDA)) are gradually increased, memory volumes required by these information electronic products become greater. Regarding the situation that the memory size becomes smaller and the memory volume is required to be increased, to fabricate a memory device with a small size, a high integrity and a high quality is a common object for the semiconductor industry.
Since a non-volatile memory device has an advantage of still maintaining stored data even if the power is cut off, it becomes a memory device widely used by personal computers and electronic equipments.
In a typical non-volatile memory device, doped polysilicon is used to fabricate a floating gate and a control gate to form a stacked structure. Dielectric layers are respectively disposed between the floating gate and a substrate, and between the floating gate and the control gate.
However, multiple polysilicon layers and multiple dielectric layers are required to be formed in the above non-volatile memory. During the fabrication process, a plurality of mask processes is performed, so that a fabrication flow is prolonged, and a fabrication cost thereof is increased.
A U.S. Pat. No. 6,678,190 discloses a non-volatile memory, in which it is unnecessary to form the multiple polysilicon layers, and two connected P-type metal-oxide semiconductor transistors disposed on N-well respectively serve as a select transistor and a floating gate transistor. Since only a single layer of polysilicon is required, a fabrication process of such non-volatile memory can be integrated with a complementary metal-oxide semiconductor transistor, so as to reduce the fabrication cost.
However, in the non-volatile memory disclosed by the U.S. Pat. No. 6,678,190, since one of the P-type metal-oxide semiconductor transistors has to serve as the select transistor, a size of the memory cell cannot be further reduced.
However, with the development of the integrated circuit industry, fabricating smaller products with a higher speed becomes the general object in this field. Therefore, the integration of the memory device certainly will be increased continuously.
However, the reduced line width often causes the short channel effect, which results in the drop of the threshold voltage (Vt) of the device and poor controlling of the gate voltage (Vg) to the memory cell, and besides, the hot electron effect also occurs, as the channel size is reduced, thus adversely influencing the operation of the memory device. All the problems cause misjudgement of the data by the memory, thus reducing the reliability of the memory. Therefore, it can be seen that, how to form a memory with high integration and high reliability has become an urgent problem to be solved.